1. Field of the Invention
The present invention concerns an integrated circuit having a first in, first out memory (FIFO).
2. Description of the Prior Art
First in, first out memories (FIFOs) are commonly used in systems to facilitate communications between a device that writes into the FIFO, and a device that reads from the FIFO. These devices often operate asynchronously to one another, with the FIFO providing a buffer memory between them. (However, synchronous systems may also use a FIFO). Often, a dual-port memory array is used to implement the FIFO memory, with a first port serving as the read port, and the second port serving as the write port. This conveniently allows for simultaneously reading from, and writing into, separate memory locations. (However, designs using single-port memories are also known.) Although various physical configurations are possible, the FIFO memory array for illustrative purposes may be considered a series of adjacent memory cells, each specified by a unique address. The write operation starts at the first memory location, and proceeds in sequence through all the adjacent memory locations until reaching the end location. Then, the write operation begins again at the first location, thereby cycling repetitively through the memory array. Similarly, the read operation cycles repetitively through the memory array.
However, the read operation must not advance to a location beyond that which has been written into in the current cycle, or else old data (from an earlier cycle) will be read. It is often said that a write "pointer" marks the memory location currently selected for writing, while a read "pointer" marks the memory location currently selected for reading. Some method of generating pointers (i.e., selecting memory locations) must be provided, and also some method must be provided for keeping track of the pointers, at least to the extent of ensuring that the read pointer does not advance beyond the write pointer. For this purpose, a "flag" is normally generated when both pointers advance to the same memory location. A "full" flag indicates that the write pointer has advanced one complete cycle beyond the read pointer. Hence, the microprocessor or other circuitry that writes into the FIFO is instructed to halt operation until the FIFO has been read. Similarly, an "empty" flag indicates that the read pointer has advanced up to the same location (or the next adjacent location) as the write pointer, so that all of the information previously stored in the FIFO has been read out. Then, the microprocessor or other circuitry that reads from the FIFO is instructed to halt until more information had been written into the FIFO, thereby preventing old information from being erroneously read as current information. It is also known to generate partially-full (e.g., half-full) flags for various control purposes.
One prior-art "first in, first out" (FIFO) memory architecture requires counters, separate from the dual-port memory block, to generate read and write addresses. These addresses are decoded to access particular words in the dual-port memory, and are compared to generate the full and empty flags. However, the prior-art address generators and flag generators are not incorporated into the memory block, thereby requiring individual layout for each different size FIFO, and having a negative impact on performance and design cycle time. Another known type of FIFO memory architecture uses shift registers to sequence the read and write address by advancing a "1" through either shift register to indicate the present address; see, for example, U.S. Pat. No. 4,535,427 for one such design. In that technique, each bit of the read and write side shift register accesses a distinct word line from the dual-port memory. However, the prior-art still required the use of counters to generate the full and empty flags.